The Verification Gap

Functional verification is a severe bottleneck in chip design projects. The ever-growing chip density and complexity impacts the time it takes simulators to complete each run. In some applications simulations can take days to complete, affecting the product’s time-to-market or forcing tape-out before full testing is completed.

Complementing Simulators with Multicore Processor Acceleration
RocketSim solves the simulator’s bottleneck challenge by offloading most time-consuming calculations to an ultra-fast multithreaded engine running on standard servers using either multicore CPU or GPU. Unlike hardware based accelerators, RocketSim works from within the familiar simulator environment and runs alongside the existing test bench, eliminating ramp-up time while providing bit-precise results.  

Enabling Full Debug Visibility for Large Designs 
RocketSim supports large and complex designs (over one billion gates), while offering full visibility of your design. Thanks to its very efficient memory utilization, you can finally expand your current verification scope to include larger designs and to verify more complex tests.

Runs from within the Simulator Environment
RocketSim is transparent to the user, who continues to use the existing simulator. Working from within the familiar host simulator environment, RocketSim supports any user PLI modules, runs PLI put/get/force values from signals and RAMs as part of its acceleration, and can run alongside the existing test bench.

Main Features

  • Accelerates functional Verilog simulation by over 10X
  • Reduces host memory footprint by over 5X
  • Compatible with the leading simulators
  • Fast compilation of large designs
  • Full debug visibility (VCD, FSDB)
  • Over billion gate capacity
  • Four-state logic
  • Compliant with Verilog IEEE 1364-2001, 1364-2005, VHDL, System Verilog,
    OVM, VMM and UVM.
  • PLI-compliant interface
  • Runs alongside the test bench